Mastering AI Chip Complexity
Explore challenges and solutions in AI chip development
Download eBook
High-Performance Emulation for Complex Designs
Synopsys ZeBu? EP is a high-performance, scalable, unified hardware platform for emulation and prototyping to validate long software workloads for billion+ gate designs. Growing software, silicon, and system complexity requires hardware-assisted verification solutions to achieve first pass silicon success. ZeBu EP's performance and capacity scaling support the key use cases for verification and validation needed to achieve that success. Along with performance and scalability, ZeBu EP supports the largest library of transactor models, memory models, and speed adaptors to run demanding workloads such as AI, networking, and evolving architectures.
Features & Benefits
- Capacity scaling supports up to 5.8 billion gates (for ZeBu EP2) and up to 1.28 BG (for ZeBu EP1)
- High-performance platform supporting petacycle workloads required for complex systems and SoCs
- Support for key hardware-assisted verification use cases including early RTL verification and regression, SW bring-up, power and performance analysis, and SW/HW validation
- Low cost of ownership with single hardware platform
ZeBu EP2
ZeBu EP1
Configurability for all Emulation and Prototyping Use Cases
ZeBu EP is built on an EP-Ready Hardware Platform that allows to reconfiguration to support HAPS prototyping and HAPS Protocompiler. Read more in our blog.
Users tend to do a lot of targeted functional verification as the RTL starts to come together. They need a platform that makes it easy and quick to port over their simulation environments and provide enough acceleration to cover the scenarios that are not ideal for simulation and formal environments. ZeBu’s simulation acceleration capabilities are utilized by industry’s major GPU, CPU, NPU, TPU providers along with other IP vendors in the networking, automotive sectors.
As RTL matures, users desire a platform that can provide orders of magnitude faster performance to cover long running suites. These regression suites serve the dual purpose of proving functional correctness, as well as getting closer to targets for coverage metrics. ZeBu’s transaction-based high-performance platform combines with its strong suite of industry’s latest Protocol Solutions (Transactor and Speed Adapters) to address these needs at some of the largest chip companies.
Starting from a reasonable level of RTL maturity, users start bringing up their software environments. There is a mix of bare-metal, low-level drivers and firmware, operating systems like Linux-Windows-Android, benchmark software application, general-purpose user applications that need to be brought up and proven functional. As the user persona evolves from being hardware-centric to a mix of hardware and software, ZeBu brings capabilities like Virtual Host Solutions to make the software developer feel at home. Combined with its superior performance, users can get very close to silicon like behavior.
As the designs near tape-out schedules, validation engineers get into a mode of mimicking their post-silicon lab environments. Their primary requirement is to enable hardware and software developers with a platform that could be used to serve as the highest-performance option in pre-silicon testing using real-world interfaces. They also want to build this platform as an option to reproduce and debug issues that they would encounter in the lab. Visibility into the design and being able to deterministically repeat those scenarios is key. ZeBu comes with a suite of strong debug technologies as well as a wide suite of speed adapters that have proven a capable partner for users to identify bugs and resolve them timely to not impact the customer’s time-to-market.
Users turn their attention to key design attributes of power and performance. They have long-running workloads that heavily exercise the DUT. By design, ZeBu can accurately model large number of clock domains prevalent in the modern SoC environments and yet provide the performance to execute these workloads.
What Our Customers Are Saying
"Investing in a scalable, single hardware platform for emulation and prototyping provides a significant economic advantage. As our storage designs typically involve many different products variants for many different applications, we are looking forward to continuing to benefit from the ZeBu EP product family for greater flexibility in our hardware resources as well as the scalable capacity it provides as we switch between emulation and prototyping.”
Vincent Cheng
|Engineering Vice President, Phison
"The future of emulation and prototyping demands unprecedented performance, adaptability, and scalability. By integrating the AMD Versal Premium VP1902 adaptive SoC, with its industry-leading capacity*, performance, and debug capabilities, into Synopsys' EP-Ready platforms we're not only improving performance metrics, we're also transforming how engineering teams can validate and optimize their most ambitious new ASIC and SoC designs. Our longstanding partnership with Synopsys empowers design teams to tackle their most complex verification challenges, from AI/ML workloads to multi-die architectures, while dramatically accelerating time to market.”
Salil Raje
|Sr Vice President and General Manager, Adaptive and Embedded Computing Group, AMD
*Based on AMD internal analysis in May 2023 with a 6-input LUT count to compare the Versal Premium VP1902 device versus competitor offerings.
"Validating our multi-die design against real-world interfaces and scenarios with the high-performance HAPS prototyping platform enables us to optimize our design early on, with faster build times and more predictable results. Having a common hardware platform for different prototype models means we can shift the hardware to use on large or small models in real time, with reduced compute and storage resources and the ability to easily and quickly scale as our needs require."
Lam Ngo
|Principal Engineer, Microsoft
"AMD has used ZeBu EP solutions for fast emulation with software workloads for a number of years. The Synopsys EP-Ready Hardware concept has allowed us to switch on demand, as a design matures, to a prototyping use case and significantly increase workload throughput. ZeBu-200 and HAPS-200 EP-Ready systems will enable further performance improvements to accelerate design verification and software validation.”
Alex Starr
|Corporate Fellow, AMD
